We are now looking for interns to join our ASIC Physical Design team located in Shanghai.
What you'll be doing:
* Chip integration and netlist generation
* RTL/netlist quality check
* Formal Verification
* Constraints creation and validation, timing budget.
* Work with ASIC team to analyze/resolve timing issues.
* Co-work with PR engineers to implement chip partition and floorplan
* Work on full chip and all child levels timing closure and signoff
* Achieve special timing closure, such as io, test, clock, async etc.
* Function eco creation
* Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)
* Flow automation development for above areas
* Methodology in any of above areas.
What we need to see:
* MS in EE or Microelectronics is preferred
* Courses taken in circuit design, digital IC design
Ways to stand out from the crowd:
* Excellent English communication skill
* Proficient user of Perl or TCL is preferred