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AMS Design Verification Intern - Metamorphic Relation-Based Verification Flow (m

Company not shown
Germany  Munich, Germany
Internship, Arts/Creative/Design, English

Job Description:

class="jd__row--main jd__summary--main" data-reactid="101">Imagine what you could do here. At (COMPANY NAME), new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Multifaceted, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all (COMPANY NAME) Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking (COMPANY NAME) product! The AMS IP team is responsible for a wide portfolio of IPs & complete subsystems going to all the (COMPANY NAME) products. In this context the Design Verification Engineer collaborates with many different teams at (COMPANY NAME) and builds knowledge of many chips & platforms in order to bring system-level understanding into the verification flow. The responsibility goes end-to- end: starting at the specification level, defining verification strategy & plan, carrying out the verification, doing performance analysis, and handling all the different quality metrics to signoff the verification.

Key Qualifications
Key Qualifications

* Knowledge of Object Oriented Programming
* Knowledge of Verilog and/or VHDL
* Scripting language knowledge (perl/python)
* Good written and verbal communication skills
* Excellent interpersonal skills and well-organised working style
* Ability to work well in an international team and be productive under tight schedules
* Availability for at least 6 months


This internship requires a good knowledge of digital signal processing in general as well as a good background in OOP. With mentorship, you will have to learn & analyse the verification flow & methodology used for IP verification and develop a reusable methodology, based on metamorphic relations, to verify a typical signal processing block inside mixed-signal systems. Your tasks include the following: - Learn UVM-based verification methodology - Define and design metamorphic relation based verification flow - Design of self-checking tests for standard compliance testing

Education & Experience
Education & Experience

Currently enrolled in your penultimate year of studies in a CE, EE, CS or related field (Bachelor's, Master's or PhD).

Additional Requirements
Additional Requirements

* (COMPANY NAME) is an Equal Opportunity Employer committed to inclusion and diversity. We take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities

Source: Company website
Posted on: 13 Oct 2021
Type of job: Internship
Industry: Consumer Electronics
Languages: English
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