PMU Analog Layout Design Intern (m/f/d)

Description du poste:

The Silicon Engineering team is looking for a motivated intern (m/f/d) in Custom Analog Layout who wants to gain hands-on experience in chip design. You will support our Power Management team in developing analog ICs that power millions of Apple products around the world. Working closely with experienced layout engineers and circuit designers, you'll get exposure to the full layout and verification flow used in modern sub-micron CMOS technologies.\",\"description\":\"* Support transistor-level layout of analog circuit blocks under the guidance of experienced colleagues\\n* Assist with layout verification (DRC, LVS, PERC, DFM) using Siemens EDA (Calibre)\\n* Gain insight into block- and top-level floor-planning together with the design team\\n* Analyse and document layout results and support design reviews\\n* Learn layout techniques for device matching, minimising parasitics, and power routing\",\"preferredQualifications\":\"Ideally some initial exposure to layout tools such as Cadence Virtuoso or similar full-custom environments\",\"minimumQualifications\":\"Currently enrolled student (m/f/d) in Electrical Engineering, Microelectronics, or a related field\\nBasic knowledge of semiconductor technology / CMOS circuits, e.g. from coursework or projects\\nAnalytical mindset, attention to detail, and enjoyment of precise, hands-on work\\nBasic familiarity with Unix/Linux command-line environments\\nEnglish language fluency (both written and verbal)\\nTeam player with strong communication skills for working across disciplines