Optimization of a Keccak Hardware Accelerator Protected against Side-Channel Attacks H/F

Description du poste:

Position description

Category

Electronics components and equipments

Contract

Internship

Job title

Optimization of a Keccak Hardware Accelerator Protected against Side-Channel Attacks H/F

Subject

With the advent of Post-Quantum Cryptography (PQC), new cryptographic standards rely heavily on complex mathematical operations that must remain secure even against quantum computers. However, their implementations are vulnerable to side-channel attacks, which exploit physical leakages such as power or electromagnetic emissions to recover secret information. Masking countermeasures mitigate these attacks by splitting sensitive data into random shares, ensuring that no single computation reveals useful information to an attacker.

Contract duration (months)

6

Job description

The objective of this internship is to optimize a first-order masked Keccak accelerator implementing Domain Oriented Masking (DOM) for protection against side-channel attacks. The work focuses on reducing both the hardware area and the amount of randomness required by the countermeasure, without compromising security. Starting from the existing masked SHA-3 accelerator developed at CEA [1], the student will analyze the main sources of area overhead introduced by the masking and randomness generation mechanisms. Based on this analysis, alternative micro-architectural solutions for the non-linear Keccak steps and the randomness dispatcher will be investigated to improve efficiency. The optimized design will be modeled in HDL and synthesized on FPGA or ASIC targets to evaluate cost, performance, and scalability. Security validation will be conducted using Test Vector Leakage Assessment (TVLA). The expected outcome is a more compact and resource-efficient masked Keccak accelerator that maintains first-order resistance, enabling practical deployment of secure SHA-3 hardware in post-quantum cryptographic systems.

Applicant Profile

This offer is dedicated to master students looking for an ambitious research-oriented internship. If you are looking for an experience in ASIC and FPGA design with industrial-grade tools and processes, this internship is perfect for you! It is required to have graduate-level experience in FPGA and ASIC design and be familiar with arithmetic circuit microarchitectures, RTL modelling (VHDL or Verilog/SystemVerilog) and synthesis (Synopsys Design Compiler, Xilinx Vivado).

Position location

Site

Grenoble

Job location

France, Auvergne-Rhône-Alpes, Isère (38)

Location

Grenoble