Thesis Internship-Design and implementation of an arithmetic accelerator for Elliptic Curve Cryptography (ECC) and RSA operations

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Design, implementation, and testing of a hardware unit capable of performing big integer arithmetic operations, targeting the acceleration of ECC and RSA cryptography in resource-constrained domains, such as IoT and microcontroller devices.
Internship activities:
* Define the architecture of the accelerator starting from existing reference points, including sizing the arithmetic unit, designing the control unit, mapping memory, and chaining low-level operations for cryptographic applications.
* Implement the accelerator using a hardware description language (HDL), including integration on a system bus.
* Design a test bench for the accelerator and benchmark its performance.
* Possibility to explore FPGA synthesis, mapping, and integration with software stacks (optional).
Requirements:
* Knowledge of cryptography concepts and computer arithmetic.
* Experience with hardware design using languages such as VHDL and SystemVerilog.
* Direct experience with ECC or RSA implementations is a plus.
You will work in an international team, based in Italy and France, with strong expertise in cryptographic implementations, both hardware and software, and microcontroller security.
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