ASIC Verification Engineer

Descrizione del lavoro:

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ASIC Verification Engineer Responsibilities

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Develop and execute verification plans for ASIC designs, ensuring comprehensive coverage and validation of design specifications.

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Collaborate with design engineers to understand design intent and identify potential verification challenges.

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Create and maintain testbenches and test cases using industry-standard verification languages and methodologies (e.g.

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SystemVerilog, UVM).

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Perform simulation and debugging of ASIC designs to identify and resolve functional issues.

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Analyze and document verification results, providing feedback and recommendations for design improvements.

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Participate in design and verification reviews, contributing to the continuous improvement of verification processes and methodologies.

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Work closely with cross-functional teams, including design, architecture, and firmware, to ensure successful integration and functionality of ASIC designs.

Minimum Qualifications

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Master's degree (or foreign equivalent) in Electrical Engineering, Computer Engineering or a related field

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Requires completion of a university-level course, research project, internship, or thesis in the following:

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Developing and executing verification plans for digital designs

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Using hardware description languages (e.g. Verilog) and verification languages (e.g. SystemVerilog) with in UVM (Universal Verification Methodology)

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Creating and maintaining testbenches and test cases for ASIC verification

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Debugging and resolving issues in digital designs through simulation and analysis

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Understanding of digital design concepts and methodologies

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Collaborating across design, emulation, and silicon validation teams for the development of robust test benches using SystemVerilog, and UVM methodologies

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Using scripting skills in Python for test automation, environment setup, and process optimization

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Utilizing EDA tools for simulation and verification (e.g. Cadence, Synopsys, Mentor Graphics)

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Documenting verification processes and results for review and analysis and

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Engaging in design and verification review to analyze verification results, identify design issues, provide technical feedback, and recommend improvements to verification strategies and test plans

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