Cellular Baseband Design Verification Intern

Descrizione del lavoro:

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products very quickly. Bring your passion and curiosity, and there's no telling what you could accomplish. Do you love working on challenges that no one has solved yet? Join us to help deliver the next groundbreaking Apple product!\\nThe Cellular Baseband DV team in Munich verifies the modems and transceiver link controllers that keep millions of people connected, wherever they are. As an intern, you'll be at the centre of a chip design effort, working with architects and designers to make sure that when someone's call, stream or message goes through, it just works.\",\"description\":\"As a Design Verification Intern, you'll be part of our silicon design group's verification efforts, helping ensure the quality and reliability of next-generation cellular systems. Working on baseband modems and RF link controllers for Apple's SoCs, you'll contribute to reusable UVM verification environments and help develop coverage-driven and directed test cases that validate complex IP and subsystem designs. You'll work closely with multi-functional teams and receive hands-on mentorship throughout the internship.\\nThis internship offers an opportunity to build expertise in cellular protocols, complex IP and subsystem architectures, fabric protocols, and debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures. You'll also explore how LLMs and ML-based tools can improve verification productivity.\\nWe're looking for motivated students with a strong foundation in digital design and programming, and an interest in ASIC design verification. You thrive in collaborative environments, pay attention to detail, and are eager to take on the verification challenges of complex, high-performance cellular systems.\",\"responsibilities\":\"Contribute to detailed test plans for components of the design, including use cases, in collaboration with multi-functional teams.\\nHelp create coverage-driven verification plans from specifications and work to achieve coverage targets.\\nDevelop components of UVM-based, reusable testbenches, such as stimulus, checkers, VIPs and reference models.\\nImplement tests from RTL simulation bring-up onwards; report and debug failures.\\nRun regressions and report verification progress against test plans and coverage metrics.\\nBuild Python-based automation to improve team productivity.\\nExplore the use of Large Language Models (LLMs) and ML-driven workflows to improve the efficiency and quality of verification.\\nDocument your work and present your results to the team at the end of the internship.\",\"preferredQualifications\":\"Knowledge of UVM and SystemVerilog Assertions (SVA).\\nExperience with SystemC and C/C++ modeling for design verification.\\nPython or Perl scripting and automation experience.\\nKnowledge of 4G/5G cellular physical layer operation (3GPP).\\nFamiliarity with bus fabrics and protocols such as AHB, AXI or NoC.\\nFamiliarity with embedded processor cores.\\nExperience using LLMs to improve productivity, including prompt engineering and LLM workflow optimization.\",\"minimumQualifications\":\"Currently enrolled in Masters in Electrical Engineering, Computer Engineering, Computer Science, Communications Engineering or a related field.\\nKnowledge of digital design fundamentals and SystemVerilog / Verilog.\\nProgramming experience in C/C++ and/or Python.\\nUnderstanding of verification concepts such as constrained-random testing and coverage-driven verification.\\nTest planning and problem-solving skills.\\nFluent in English (written and verbal)