“PhD thesis (CIFRE) at STMicroelectronics in Panel-Level Packaging (PLP) interface characterization. Focus on mechanical behavior, adhesion, and delamination mechanisms. Collaboration with University of Tours. Requires Master's in Physics/Materials/Chemistry. Full-time on-site in France.”
“Offer for a regular job in embedded cybersecurity verification & validation (V&V) post-degree. Role involves functional verification, secure boot validation, cryptographic core testing, and debugging on microcontrollers. Requires Python/C skills, ISO 26262 knowledge, and embedded systems expertise. Based in Italy (Italian/English).”
“PhD position (CIFRE) at STMicroelectronics in collaboration with CEA, focusing on laser fault injection models for semiconductor security. Requires microelectronics, physics, and analog electronics knowledge. Based in France, includes experimental work on FDSOI/P18nm chips.”
“PhD position (CIFRE) at STMicroelectronics for 3 years in multiscale electro-thermal modeling of silicon power devices. Focus on coupled simulations (TCAD/COMSOL) to predict self-heating, current crowding, and SOA limits in MOSFETs for automotive applications. Requires Master's in semiconductor physics/electronics, strong interest in numerical simulation, and scientific English proficiency.”
STMicroelectronics | Tours
|Graduate Programme, Research, English, French
“CIFRE PhD position at STMicroelectronics (3 years) in semiconductor physics focusing on cosmic ray robustness for silicon carbide devices. Requires a Master's degree, finite-elements simulation skills, and B2 English. Collaboration with CNES for heavy-ion testing and analysis of diode structures.”
“Process Engineer role in dry etching at ST, a global semiconductor company. Responsibilities include machine performance, troubleshooting, data analysis, and quality assurance. Requires degree in STEM fields, English proficiency, and teamwork. Based in Italy (likely).”
“Thèse CIFRE chez STMicroelectronics en partenariat avec QUOBLY pour concevoir des architectures de qubits de spin en silicium (FDSOI CMOS) pour calcul quantique. Missions : simulation 3D, caractérisation cryogénique, optimisation de layout. Profil recherché : Bac+5 en micro/nanoélectronique ou physique quantique, compétences en dispositifs MOSFET et salle blanche. Contrat de 3 ans basé en France.”
