Analog Mixed-Signal Verification Engineer

Descrizione del lavoro:

ELSYS Design est une société d'ingénierie spécialisée dans la conception des systèmes électroniques embarqués (microélectronique, carte électronique, logiciel embarqué, ingénierie système). Présent sur 14 sites en Europe et aux États-Unis, ELSYS Design propose des solutions entièrement personnalisées pour accélérer les projets de R&D de ses clients grâce à une expertise multisectorielle et des modèles d'intervention flexibles. Fondée et managée par des ingénieurs, c'est une filiale d'ADVANS Group.
At Advans, we support clients across a wide range of industries - including energy, semiconductors, defense, aerospace, transportation, and more - through four core areas of expertise: microelectronics (FPGA, ASIC, SoC), electronic boards, embedded software, and systems engineering. As a AMS Verification Engineer, you will join a team working on complex Analog Mixed-Signal (AMS) ASIC products, under the guidance of the AMS Verification Leader and alongside experienced verification engineers. This role is a great opportunity for a engineer looking to develop strong expertise in AMS verification, mixed-signal modeling, and ASIC verification methodologies within challenging semiconductor projects. Your main responsibilities AMS Verification Contribute to the verification of AMS IPs at IP and top level Support the execution of verification plans for DC/DC converter IPs and their integration Participate in coverage analysis and verification closure activities Help debug and analyze simulation issues System-Level AMS Verification Contribute to the development and maintenance of AMS Top Cell verification environments Help verify consistency between behavioral models and transistor-level implementations Participate in the validation of analog/digital interactions at system level Modeling and Abstraction Contribute to AMS model development using wreal (Real Number Modeling) Participate in model creation using Verilog-AMS and SystemVerilog RNM Learn to structure models based on physical quantities such as voltage, current, and impedance Digital Verification Integration Contribute to SystemVerilog / UVM verification environments Support the integration of AMS models into digital verification testbenches Participate in regression execution, test development, and debug Protocols and Interfaces Contribute to the modeling and verification of interfaces such as PSI5 Team Collaboration Work closely with design, architecture, validation, and verification teams Participate in design and verification reviews Learn from experienced engineers and progressively grow your autonomy

Requisiti del candidato:

Profile we are looking for

Education

Master's degree or Engineering degree in Electronics, Microelectronics, or Embedded Systems

Experience

Minimum 1 year of experience (including internships or first professional experience) in AMS verification, ASIC design, or mixed-signal environment
A first exposure to semiconductor verification methodologies is appreciated
Technical skills
The following skills are considered a strong plus:
Knowledge of AMS verification principles
First experience or academic exposure to mixed-signal modeling
Familiarity with wreal, Verilog-AMS, or SystemVerilog RNM
Basic understanding of physical quantities such as voltage, current, and impedance
Knowledge of SystemVerilog / UVM
Exposure to DC/DC converters or power management concepts
Familiarity with PSI5 or similar interfaces
Knowledge of Cadence, Synopsys, or equivalent AMS simulation tools
Soft skills
Analytical mindset and strong curiosity
Eagerness to learn and grow technically
Good communication and teamwork skills
Autonomous, rigorous, and quality-oriented
Interest in complex semiconductor systems
Nice to have
Exposure to automotive applications
Awareness of functional safety standards (ISO 26262)
Benefits
Integration program in a professional, young & dynamic team
Professional development opportunities
Health insurance
International work environment