Formal Verification Framework for Hardware IPs Validation

Descrizione del lavoro:

Join a rapidly growing team at our London design center. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly. \\nThe AMS IP team owns a wide portfolio of IPs \u0026 complete subsystems going to all the Apple products. In this context the Design Verification Engineer will have to interface with many different teams at Apple and build knowledge of many chips \u0026 platforms in order to bring system-level understanding into the verification flow. The responsibility goes end-to-end: starting at the specification level, defining the verification strategy \u0026 plan, executing the verification, doing performance analysis and handling all the different quality metrics to signoff the verification.\",\"description\":\"Define comprehensive property sets for functional coverage of hardware models \\nFormalize verification properties using SVA\\nExecute formal proofs and analyze convergence behavior (accuracy VS execution time)\\nDocument methodology and best practices for the verification flow\",\"responsibilities\":\"This internship would require a strong foundation in formal verification methodologies, good mathematical reasoning as well as some knowledge in hardware modeling. The intern will work on developing comprehensive property sets to achieve functional coverage of hardware models. The focus will be on formalizing properties in SVA and executing formal proofs using industry-standard tools. A key challenge will be identifying optimal trade-offs between model accuracy and proof convergence times. \\nThe intern will then extend the verification framework in order to integrate the properties at higher levels to enable system verification.\",\"preferredQualifications\":\"Master's / Bachelor's in Computer Science or equivalent\\nYou are available for 6 months or more\",\"minimumQualifications\":\"Currently enrolled in Computer Science or equivalent \\nKnowledge of formal verification techniques\\nKnowledge of Verilog and/or VHDL\\nPassionate about mathematics, and good mathematical/analytical sense\\nScripting language knowledge (perl/python)\\nGood written and verbal communication skills \\nExperience in working with international teams