UIUC Research Park Intern - Functional Safety Hardware

Descrizione del lavoro:

About Rivian

Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.

As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.
Role Summary

Internship Term: Summer 2026

Rivian internships are experiences optimized for student candidates. To be eligible, you must be an undergraduate or graduate student in an accredited program during the internship term with an expected graduation date between December 2028 through May 2028. Rivian's Internship Program requires active student enrollment. Information regarding your expected degree completion date is collected solely to verify eligibility and determine your availability for future full-time opportunities. Rivian is an equal opportunity employer and does not use graduation dates to determine the age of applicants or as a basis for discriminatory hiring decisions.

If you are not pursuing a degree, please see our full time positions on our Rivian careers site.

Note that if your university has specific requirements for internship programs, it is your responsibility to fulfill those requirements.

We are looking for a detail-oriented Hardware Functional Safety Engineer to join our engineering team. In this role, you will be at the front lines of ensuring our next-generation safety-critical systems-specifically High-Performance SoCs and complex PCBs-are robust enough to handle the rigors of real-world deployment. You will focus on identifying potential failure points through rigorous systematic analysis, ensuring that our hardware designs are resilient against both random hardware failures and common-cause dependencies.
Responsibilities

* Your primary focus will be supporting the functional safety lifecycle for hardware components through quantitative and qualitative analysis.

* FTA (Fault Tree Analysis): Support top-down FTA to identify combinations of hardware failures that could lead to a violation of safety goals. You will help build logic trees to visualize and quantify the probability of catastrophic system failures.

* DFA (Dependent Failure Analysis): Conduct DFA to identify potential "freedom from interference" issues. You will analyze shared resources (e.g., clock trees, power rails, or physical proximity on a PCB) to identify Cascading Failures and Common Cause Failures (CCF) that could bypass safety redundancies.

* FMEDA (Failure Modes, Effects, and Diagnostic Analysis): Assist in performing quantitative FMEDA to calculate hardware architectural metrics (SPFM, LFM) and the Probabilistic Metric for random Hardware Failures (PMHF). You will evaluate the effectiveness of safety mechanisms in detecting or controlling hardware faults.

* Design Review: Review hardware requirements and schematics to ensure safety mechanisms (e.g., ECC, parity, redundant paths, voltage monitors) are correctly implemented to mitigate the faults identified in your FTA and DFA.

* Documentation: Contribute to the creation of Work Products required by ISO 26262, such as the Hardware Safety Analysis Report and Safety Case fragments
Qualifications

* Must be currently pursuing a bachelors, masters, or PhD degree at the University of Illinois Urbana Champaign
* Actively pursuing a degree or one closely related in Electrical Engineering or Computer Engineering
* Foundational knowledge of ISO 26262 (specifically Parts 5, 9, and 11)
* Understanding of FTA (Qualitative/Quantitative) and the principles of DFA
* Ability to read and interpret PCB schematics and understand SoC internal blocks (CPUs, Interconnects, Memory)
* A "safety-first" mindset, extreme attention to detail, and the ability to explain complex failure modes to design engineers.

* Experience with safety analysis tools (e.g., Ansys medini analyze, Item Toolkit, or Reliability Workbench), preferred.
* Knowledge of ASIL (Automotive Safety Integrity Level) decomposition strategies, preferred.
* Familiarity with hardware description languages (Verilog/VHDL) or hardware verification.
* Practical experience with physical layout constraints that impact DFA (e.g., substrate isolation, power domain separation), preferred.

#LI-HH2
Pay Disclosure

The salary range for this role is $25.00-40.00 per hour for Normal based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee's position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.

We offer a comprehensive package of benefits including but not limited to paid vacation, paid sick leave, and medical insurance benefits. More information about benefits is available at rivianbenefits.com.

You can apply for this role through careers.rivian.com (or through internal-careers-rivian.icims.com if you are a current employee). This job is not expected to be closed any sooner than 4/10/2026.
Internship positions are not eligible for retirement benefits.

Equal Opportunity

Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law.

Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at candidateaccommodations@rivian.com.

Candidate Data Privacy

Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes ("Candidate Personal Data"). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law.

Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian's service providers, including providers of background checks, staffing services, and cloud services.

Rivian may transfer or store internationally your Candidate Personal Data, including to or in the United States, Canada, the United Kingdom, and the European Union and in the cloud, and this data may be subject to the laws and accessible to the courts, law enforcement and national security authorities of such jurisdictions.

Please note that we are currently not accepting applications from third party application services.

* Your primary focus will be supporting the functional safety lifecycle for hardware components through quantitative and qualitative analysis.

* FTA (Fault Tree Analysis): Support top-down FTA to identify combinations of hardware failures that could lead to a violation of safety goals. You will help build logic trees to visualize and quantify the probability of catastrophic system failures.

* DFA (Dependent Failure Analysis): Conduct DFA to identify potential "freedom from interference" issues. You will analyze shared resources (e.g., clock trees, power rails, or physical proximity on a PCB) to identify Cascading Failures and Common Cause Failures (CCF) that could bypass safety redundancies.

* FMEDA (Failure Modes, Effects, and Diagnostic Analysis): Assist in performing quantitative FMEDA to calculate hardware architectural metrics (SPFM, LFM) and the Probabilistic Metric for random Hardware Failures (PMHF). You will evaluate the effectiveness of safety mechanisms in detecting or controlling hardware faults.

* Design Review: Review hardware requirements and schematics to ensure safety mechanisms (e.g., ECC, parity, redundant paths, voltage monitors) are correctly implemented to mitigate the faults identified in your FTA and DFA.

* Documentation: Contribute to the creation of Work Products required by ISO 26262, such as the Hardware Safety Analysis Report and Safety Case fragments

Requisiti del candidato:

* Must be currently pursuing a bachelors, masters, or PhD degree at the University of Illinois Urbana Champaign
* Actively pursuing a degree or one closely related in Electrical Engineering or Computer Engineering
* Foundational knowledge of ISO 26262 (specifically Parts 5, 9, and 11)
* Understanding of FTA (Qualitative/Quantitative) and the principles of DFA
* Ability to read and interpret PCB schematics and understand SoC internal blocks (CPUs, Interconnects, Memory)
* A "safety-first" mindset, extreme attention to detail, and the ability to explain complex failure modes to design engineers.

* Experience with safety analysis tools (e.g., Ansys medini analyze, Item Toolkit, or Reliability Workbench), preferred.
* Knowledge of ASIL (Automotive Safety Integrity Level) decomposition strategies, preferred.
* Familiarity with hardware description languages (Verilog/VHDL) or hardware verification.
* Practical experience with physical layout constraints that impact DFA (e.g., substrate isolation, power domain separation), preferred.

#LI-HH2